1. Field of Invention
This invention relates to a semiconductor device and operation thereof, and more particularly relates to structure of a storage unit of a single-conductor non-volatile memory cell and a method of erasing the same.
2. Description of Related Art
A traditional non-volatile memory cell is based on a stacked gate structure that includes a floating gate and a control gate thereover. For an embedded non-volatile memory apparatus, since the peripheral circuit devices are based on CMOS transistors including only one gate layer, extra fabricating steps have to be combined with the standard CMOS process to integrate the traditional stacked-gate non-volatile memory cells and the peripheral circuit devices on one chip.
To save the extra fabricating steps in traditional embedded non-volatile memory process, single-poly non-volatile memory has been provided, wherein each memory cell includes a storage transistor including a floating gate on a tunnel layer and two source/drain (S/D) regions in the substrate beside the floating gate, wherein at least one S/D region overlaps with the floating gate. In a writing process of such a storage transistor, hot electrons are drawn into the floating gate due to a positive potential thereof induced by a positive voltage applied to the S/D region overlapping with the floating gate.
Such a storage transistor can be erased through channel Fowler-Nordheim (FN) tunneling or edge FN tunneling in the prior art. In a channel FN erasing method, as shown in FIG. 1, a quite high voltage about 20V is applied to the substrate and the S/D regions grounded, so that electrons are ejected out of the floating gate 100 through FN tunneling. In an edge FN erasing method, as shown in FIG. 2, a high voltage about 12V is applied to the source region to draw the electrons from the floating gate 200.
Since the erasing voltages are quite high, a high-voltage (HV) P-well or a deep N-well that is not seen in a standard CMOS device is required for the conventional storage transistor of N-type or P-type. The HV P-well or the deep N-well still needs extra forming steps to be combined with the standard CMOS process.